The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a multilevel interconnect structure based on a dual damascene structure that has a structural shape suitable for adoption of low dielectric constant (low-k) films as interlayer insulating films and insulating films among interconnects (interconnect insulating films), and the semiconductor device.
In step with size miniaturization and increase of integration degree of semiconductor devices, delays of electrical signals attributed to the time constant of interconnects are increasingly becoming a serious problem. Accordingly, for conductive layers in a multilevel interconnect structure, use of copper (Cu) interconnects, which have a low resistivity, has been advanced instead of aluminum (Al) alloy interconnects. The Cu, however, is difficult to pattern by dry etching unlike metal materials such as Al used in conventional multilevel interconnect structures. Therefore, typically multilevel Cu interconnect structures employ a damascene method, in which interconnect trenches are formed in insulating films, and then Cu films are buried in the interconnect trenches. In particular, a dual damascene method is attracting attention. In this method, after formation of via holes and interconnect trenches, Cu is buried in the holes and trenches simultaneously. The dual damascene method therefore is advantageous for reducing the number of steps. For example, Japanese Patent Laid-open No. Hei 11-45887 discloses this method.
In addition, in high-integration semiconductor devices, an increase of interconnect capacitance causes lowering of operation speed of the semiconductor devices. Therefore, It is essential to the semiconductor devices to employ minute multilevel interconnects for which low-k materials are used as interlayer and interconnect insulating films to suppress the increase of interconnect capacitance. Currently used as the low-k materials are substances having a dielectric constant of about 2.7, such as organic polymers typified by polyarylether (PAE) and inorganic materials typified by hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). In addition to these materials, in recent years, adoption of low-k materials having a dielectric constant of about 2.2 obtained by making the above-described materials porous is being promoted.
When the dual damascene method is applied to interlayer and interconnect insulating films including low-k material films, it is required to address the following technical restrictions.
The first restriction is that the compositions of the low-k material films are close to the composition of resist used for patterning, and therefore the low-k material films are readily damaged in a resist removal process. Specifically, it is essential that damage to the low-k material films can be suppressed in resist removal treatment after etching with use of a resist mask, and in resist reproduction treatment when a treated resist mask does not satisfy the product standard.
The second restriction is that the manufacturing process needs to have applicability to fabrication of a borderless structure, in which there is no alignment margin between interconnects and via holes. In step with miniaturization of semiconductor devices, employment of a manufacturing process compatible with a borderless structure becomes a major premise of achievement of multilevel interconnects after the 0.18 μm generation. Therefore, also in simultaneous formation, in a dual damascene method, of interconnect trenches and via holes in interlayer and interconnect insulating films including low-k materials, it is important to employ a process involving less variation in the via resistance due to misalignment.
The third restriction is that adoption of a layer with a comparatively high dielectric constant leads to an increase of interconnect capacitance. Specifically, in order to form interconnect trenches with adequately controlling the depth thereof, it is desirable to provide, near the bottoms of the interconnect trenches, a layer that has a large etching selection ratio with respect to interlayer and interconnect insulating films. However, when a layer with a comparatively high dielectric constant is used for that purpose, an increase of interconnect capacitance is caused. Therefore, there has been a need for a dual damascene process for an interlayer and interconnect insulating structure employing low-k materials, allowing control of formation of interconnect trenches combined with suppression of a capacitance increase.
As a dual damascene method that can address the above-described technical restrictions, a method has been proposed that will be described below with reference to FIGS. 7A to 7H, which are sectional views of manufacturing steps. For example, Japanese Patent Laid-open No. 2004-63859 discloses this method.
Referring initially to FIG. 7A, on a base insulating film 2 deposited on a silicon substrate 1, a multilayer film formed of a polyarylether (PAE) film 3 and a silicon dioxide film (SiO2) 4 are deposited as an interconnect insulating film. Subsequently, buried interconnects (Cu interconnects) 7 formed of a copper (Cu) film are formed in interconnect trenches 5 provided in the interconnect insulating film with the intermediary of a barrier film 6 therebetween. An etching stopper film 8 composed of silicon carbide (SiC) is then formed on the Cu interconnects 7 and the SiO2 film 4. This etching stopper film 8 also functions as a diffusion barrier film and an antioxidation film for the Cu.
Deposited on the etching stopper film 8 are a first insulating film 9 composed of MSQ, i.e., a carbon-doped silicon oxide film (SiOC film), and a second insulating film 10 composed of PAE as an organic insulating film. The formation of the films 9 and 10 is followed by sequential deposition of a first-mask forming layer 11 composed of SiO2, a second-mask forming layer 12 composed of silicon nitride (SiN), and a third-mask forming layer 13 composed of SiO2. Furthermore, a resist mask 14 having an interconnect trench pattern is formed on the third-mask forming layer 13.
Referring next to FIG. 7B, the third-mask forming layer (SiO2) 13 (see FIG. 7A) is etched by dry etching that employs the resist mask 14 (see FIG. 7A) as the etching mask, to thereby form a third mask 13′ having the interconnect trench pattern, which is then followed by ashing removal of the resist mask 14.
Referring next to FIG. 7C, a resist mask 15 having a via hole pattern is formed on the second-mask forming layer 12 and the third mask 13′. The resist mask 15 is formed so that at least part of apertures of the resist mask 15 overlaps with apertures of the interconnect trench pattern formed in the third mask 13′.
Subsequently, as shown in FIG. 7D, the third mask (SiO2) 13′, the second-mask forming layer (SiN) 12 and the first-mask forming layer (SiO2) 11 are etched by dry etching that employs the resist mask 15 (see FIG. 7C) as the etching mask. In addition, the second insulating film (PAE) 10 is also perforated, which forms via holes 16 exposing the surface of the first insulating film (SiOC) 9. The resist mask 15 is removed in the etching of the second insulating film (PAE) 10, which is an organic material. Even when the resist mask 15 is completely removed during the perforation of the second insulating film 10, the formation of the via holes 16 having a favorable aperture shape are allowed due to the second-mask forming layer (SiN) 12 (see FIG. 7C) serving as the mask, since the second-mask forming layer 12 has the pattern of the via holes 16.
Referring next to FIG. 7E, by dry etching with use of the third mask (SiO2) 13′ having the interconnect trench pattern as the etching mask, the second-mask forming layer (SiN) 12 (see FIG. 7D) having the via hole pattern is etched to thereby form a second mask 12′ having the interconnect trench pattern, and the first insulating film 9 is etched to an intermediate thickness thereof so that the via holes 16 are extended downward.
Referring next to FIG. 7F, by using the third mask (SiO2) 13′ (see FIG. 7E) and the second mask (SiN) 12′ that have the interconnect trench pattern, part of the first-mask forming layer (SiO2) 11 remaining in the interconnect trench region (see FIG. 7E) is removed to thereby form the first mask 11′ having the interconnect trench pattern. In this removal, the first insulating film (SiOC) 9 remaining under the bottoms of the via holes 16 is etched, so that the via holes 16 expose the etching stopper film 8. The third mask 13′ is removed in this etching step.
Subsequently, as shown in FIG. 7G, the etching stopper film 8 exposed through the bottoms of the via holes 16 is etched so that the via holes 16 are extended downward to reach the Cu interconnects 7, and the second mask 12′ (see FIG. 7F) is removed. Thereafter, the second insulating film (PAE) 10 remaining under the bottom of the interconnect trench pattern is etched with use of the first mask (SiO2) 11′ having the interconnect trench pattern as the etching mask. Thus, the interconnect trench pattern provided in the first mask 11′ is extended downward, which results in the formation of interconnect trenches 17 in the first mask 11′ and the second insulating film 10. Accordingly, the state is obtained in which the interconnect trenches 17 communicate with the lower Cu interconnects 7 by the via holes 16.
After the above-described steps, by posttreatment employing chemicals and RF-sputtering treatment, etching fouling that remains on sidewalls of the interconnect trenches 17 and the via holes 16 are removed, and modified layers in the surfaces of the Cu interconnects 7 at the bottoms of the via holes 16 are normalized.
Referring next to FIG. 7H, a barrier metal film 18 composed of tantalum (Ta) is deposited by sputtering in a manner of covering the inside walls of the interconnect trenches 17 and the via holes 16. Subsequently, a conductive film (not shown) composed of Cu is deposited on the barrier metal film 18 by electrolytic plating or sputtering in a manner of filling the interconnect trenches 17 and the via holes 16. Thereafter, by using chemical mechanical polishing (CMP), extra part of the conductive film and the barrier metal film 18 unnecessary for the interconnect pattern is removed, and upper part of the first mask 11′ is also removed. Thus, vias 19 composed of Cu are formed in the via holes 16 while Cu interconnects 20 are formed in the interconnect trenches 17, which allows achievement of a dual damascene multilevel interconnect structure. Moreover, an etching stopper film 21 composed of e.g. SiC is formed on the Cu interconnects 20 and the first mask 11′, similarly to the etching stopper film 8 on the lower Cu interconnects 7.
Use of this dual damascene method employing three layers of etching masks eliminates the above-described technical restrictions regarding a low-k material structure, and allows a manufacturing method in which a load associated with resist patterning steps is light.
Specifically, as shown in FIGS. 7A and 7C, reproduction treatment of the resist masks 14 and 15 that are incompatible with the product standard can be implemented on the third-mask forming layer (SiO2) 13 and the second-mask forming layer (SiN) 12. In addition, as described with reference to FIG. 7D, the removal of the resist mask 15 for opening the via holes 16 can be carried out simultaneously with the step of etching the second insulating film (PAE) 10 to extend the via holes 16. Therefore, resist removal can be implemented while suppressing damage to low-k material films.
Furthermore, as shown in FIG. 7C, the via holes 16 are formed through the third mask 13′ having the interconnect trench pattern. Therefore, when the resist mask 15 having the via hole pattern is formed, the height of steps in the underlayer thereof is as large as only the thickness of the third mask 13′. Therefore, defocusing in exposure is suppressed, which can form a resist mask having a highly accurate via hole pattern. Moreover, as shown in FIG. 7D, since the via holes 16 are formed through the third mask 13′ having the interconnect trench pattern, no variation in the size of the via holes 16 arises even if misalignment between the interconnect trenches 17 and the via holes 16 is caused.
In addition, as described with reference to FIG. 7G, when the second insulating film (PAE) 10 is etched to form the interconnect trenches 17, the etching of the second insulating film 10 is carried out on the first insulating film (SiOC) 9. Thus, a high etching selection ratio can easily be ensured. Therefore, the depth of the interconnect trenches 17 can easily be controlled without providing an etching stopper film composed of a high dielectric constant material such as an SiN film.
However, in the above-described dual damascene method, the first mask 11′, which remains among interconnects even after completion of the device, is formed of an SiO2 film. Therefore, the SiO2 film, which has a dielectric constant of about 4, remains among the interconnects. Accordingly, even if an organic insulating film such as PAE is used as a lower interconnect insulating film to reduce the dielectric constant to some extent, it is difficult to reduce the effective dielectric constant among the interconnects. Thus, it is also difficult to reduce the interconnect capacitance.
If in the above-described technique, an SiOC film (k=3.0) is used in order to reduce the interconnect capacitance instead of the SiO2 film 4 (k=4.1) serving as the insulating film among the lower Cu interconnects 7 and instead of the SiO2 film (k=4.1) of the first-mask forming layer 11 (see FIG. 7A) serving as the insulating film among the upper Cu interconnects 20, the following problem arises.
The problem will be described with reference to FIG. 8A to FIG. 9. As shown in FIG. 8A, also when an SiOC film is used for the layers 4 and 11, the manufacturing process employs the same steps as those described with FIGS. 7A to 7E, i.e., until the step in which the second mask 12′ is formed and the via holes 16 are extended downward partway across the first insulating film 9 with use of the third mask 13′ as the etching mask. The first-mask forming layer 11 is formed to have a large thickness that includes both the thickness for interconnects and the thickness of sacrificial part to be removed in a CMP step to be carried out later.
Referring next to FIG. 8B, the first-mask forming layer (SiOC) 11 (see FIG. 8A) is etched to thereby form a first mask 11′ having an interconnect trench pattern. In this step, the first insulating film (SiOC) 9 is also etched with the second insulating film (PAE) 10 with the via hole pattern serving as the mask, and therefore the via holes 16 are further extended downward so that the etching stopper film (SiC) 8 is exposed. In this etching, the etching selection ratio of SiOC to SiC (SiOC/SiC) is about 3. Since the first-mask forming layer (SiOC) 11 has a large thickness, the etching stopper film 8 is removed and thus the lower Cu interconnects 7 are exposed. Accordingly, the surfaces of the Cu interconnects 7 are susceptible to damage. In addition, in the region in which misalignment between the Cu interconnect 7 and the via hole 16 is caused, a hole A that reaches the PAE film 3 is formed in the SiOC film 4.
In the step of forming the first mask 11′, dry etching is carried out by using the third mask (SiO2) 13′ (see FIG. 8A) having the interconnect trench pattern and the second mask (SiN) 12′ as the etching mask. However, apertures of the interconnect trench pattern formed in the first-mask forming layer (SiOC) 11 become wider than the intended size. This is because the etching selection ratio of the first-mask forming layer 11 to the third and second masks 13′ and 12′ serving as the etching mask is not sufficiently high, and the first-mask forming layer 11 has a large thickness. Therefore, the thicknesses of the third and second masks 13′ and 12′ are insufficient to adequately etch the first-mask forming layer 11.
Referring next to FIG. 8C, under the above-described state, the second insulating film (PAE) 10 is etched by etching that employs the first mask 11′ as the etching mask. Thus, the interconnect trench pattern provided in the first mask 11′ is extended downward, which results in the formation of interconnect trenches 17 in the first mask 11′ and the second insulating film 10. Subsequently, the barrier metal film 18 is deposited to cover the inside walls of the interconnect trenches 17 and the via holes 16, and then the conductive film 22 is formed on the barrier metal film 18 in a manner of filling the interconnect trenches 17 and the via holes 16.
Referring next to FIG. 9, by using CMP, extra part of the conductive film 22 (see FIG. 8C) and the barrier metal film 18 unnecessary as the interconnect pattern is removed, and upper part of the first mask 11′ is also removed. Thus, vias 19 are formed in the via holes 16 while Cu interconnects 20 are formed in the interconnect trenches 17. Subsequently, an etching stopper film 21 is formed on the Cu interconnects 20 and the first mask 11′.
In the above-described manufacturing method, a void B is generated in the vias 19 and the interconnects 20 due to burying defects attributed to the hole A described with reference to FIG. 8B. Consequently, electromigration and stress migration due to the void B arise in the use environment of the semiconductor device, which deteriorates the interconnect reliability. In addition, if a hole A′ arising from widening of the hole A is generated in the SiOC film 4 and the PAE film 3 due to the subsequent etching, defects of voltage-withstanding characteristic of the interconnect insulating film arises. As one approach for overcoming this problem, increasing the thickness of the first insulating film 9 in order to prevent the generation of the hole A is also possible. However, this thickness increase leads to a higher embodiment ratio of the via holes 16 formed in the first insulating film 9. Such a high aspect ratio probably leads to insufficient burying of the conductive film 22 (see FIG. 8C) into the via holes 16, which results in conduction defects.
Furthermore, since apertures of interconnect trench pattern of the first mask 11′ are larger than the predetermined size, the widths of the interconnect trenches 17 are also larger than the predetermined size. Therefore, a sufficient voltage-withstanding characteristic between adjacent interconnects cannot be ensured, which lowers the yield of the semiconductor device. If in order to overcome this problem, the third mask 13′ (see FIG. 8A) is formed to have a large thickness and then the first-mask forming layer 11 is etched with use of the third mask 13′, the interconnect trench pattern with its size error being suppressed can be formed. However, since the via holes are extended downward in this etching with the second insulating film 10 having the via hole pattern serving as the mask, the first insulating film 9 and the etching stopper film 8 are etched, which exposes the surfaces of the Cu interconnects 7. In addition, the SiOC film 4, which is the lower layer, is also etched.
Against the above-described background, there is a need for the following manufacturing method of a semiconductor device and a semiconductor device obtained through the method. Specifically, by the method, the whole interlayer and interconnect insulating films are allowed to keep a low dielectric constant. In addition, in steps of forming interconnect trenches and via holes in the insulating films, the interconnect trenches can be formed with favorable processing controllability, without the occurrence of exposure of lower interconnects and etching of lower interconnect insulating films.